Embodiments of the invention relates generally to semiconductor nonvolatile memories, and more specifically to mitigating penalty associated with memory access.
A variety of processor-based devices including consumer devices that may be used in portable environments or otherwise, may include a semiconductor nonvolatile memory for erasably and programmably storing information. One common type of such a semiconductor nonvolatile memory is a FLASH memory or device. To operate a consumer device, generally many resident applications require a mix of code and data to be stored in such a non-volatile random access memory (NVRAM) (e.g., flash memory). For instance, wireless devices including cellular phones may utilize a flash memory that is capable of storing different forms of data associated with resident applications. Likewise, a portable device, e.g., a personal digital assistant (PDA) may incorporate a flash memory to store, among other things, certain operating system files and configurable data. Responsive to a read or a write request, access may be provided to code and/or data resident at a semiconductor nonvolatile memory (e.g., in the flash memories set forth above in connection with two exemplary processor-based devices).
However, most of the semiconductor nonvolatile memories including the flash memories have a relatively long initial access time. This long initial access time due to memory latency often prohibitively limits the maximum performance that may be obtained from many processor-based devices or systems in which the semiconductor nonvolatile memories are typically deployed.
Thus, there is a continuing need for better ways to devise semiconductor nonvolatile memories, particularly from a memory access penalty perspective.